Complimentary metal-oxide-semiconductor (CMOS) integrated circuit (IC) power reduction is important because of costs associated with wasted power. Both power related product costs (i.e., in terms of power dissipation capability to handle high temperature environments) and power related operating costs are becoming differentiations in the market. Power consumption in a digital CMOS IC is considered either static (i.e., the power consumption continues regardless of system activity) or dynamic (i.e., the power is only consumed when switching activity occurs). Static power consumption in conventional digital CMOS processes is usually the result of transistors that do not act as perfect switches. The transistors are difficult to switch off fully. The transistors remain partially on and thus allow a leakage current to flow. The leakage current results in a continuous waste of power.
Static power consumption can be mitigated by using different switching thresholds for the transistors (i.e., the “Vt” of the transistor). Transistors with a higher Vt will have worse performance (i.e., the transistor is slower to switch on and has less drive current when on). However, transistors with a higher Vt have less power leakage when switched off. Multiple libraries with different Vt values allow designers to build ICs with targeted performance/power tradeoffs. The multiple libraries are said to be footprint compatible if the libraries are otherwise identical (i.e., pin connections are in the same locations for different Vt versions of the same function).
It would be desirable to implement a method and/or apparatus for a granular channel width for power optimization.